1. Yun-Hua Tseng, Yuan-Ho Chen* and Chih-Wen Lu*, “Multiple Leads With a Switch Mode for Lossless and Lossy Compression by Using Very Large Scale Integration Technology,” IEEE Access., 2018. (SCI)

2. Yuan-Ho Chen, Szi-Wen Chen*, and Yu Juan, “Very-Large-Scale Integration Implementation of the Integral Pulse Frequency Modulation Model for Spectral Estimation of Heart Rate Variability,” Electron. Lett., 2018. (SCI)

3. Yuan-Ho Chen*, “Run-Time Calibration Scheme for the Implementation of a Robust Field-Programmable-Gate-Array-Based Time-to-Digital Converter,” International Journal of Circuit Theory and Applications, 2018. (SCI)

4. Yuan-Ho Chen, Chung-Yi Li* and Lu-An Lai, “Fine-tuning accuracy using conditional probability of the bottom sign-bit in Fixed-width Modified Booth Multiplier,” Circuits Syst. Signal Process., vol. 37, issue 7, pp. 3115-3130, July. 2018. (SCI)

5. Yun-Hua Tseng, Yuan-Ho Chen* and Chih-Wen Lu*, “Adaptive Integration of the Compressed Algorithm of CS and NPC for the ECG Signal Compressed Algorithm in VLSI Implementation,” Sensors. vol. 17, pp. 2288, Oct. 2017. (SCI)

6. Yuan-Ho Chen* and Yi-Fan Ko, “High-throughput IDCT architecture for high-efficiency video coding (HEVC),” International Journal of Circuit Theory and Applications, vol. 45, issue 12, pp. 2260-2269, Dec. 2017. (SCI)

7. Yuan-Ho Chen*, “A counting-weighted calibration method for a field-programmable-gate-array-based time-to-digital converter,” Nuclear Instruments and Methods in Physics Research Section A., vol. 854, pp. 61-63, May 2017. (SCI)

8. Yuan-Ho Chen* and Yun-Hua Tseng, “Low-cost Multi-standard Video Transform Core Using Time-distribution Scheme,” Electron. Lett., vol. 52, issue 24, pp. 1980-1982, Nov. 2016. (SCI)

9. Yun-Hua Tseng, Yuan-Ho Chen*, Tze-Yang Kao, and Chih-Wen Lu, “Low-cost Multi-Standard Simultaneous Forward and Inverse Video Transform Core,” International Journal of Circuit Theory and Applications, vol. 44, issue 8, pp. 1572-1588, Aug. 2016. (SCI)

10. Wen-Quan He, Yuan-Ho Chen*, and Shyh-Jye Jou, “Dynamic Error-compensated Fixed-Width Booth Multiplier Based on Conditional-Probability of Input Series,” Circuits Syst. Signal Process, vol. 35, no. 8, pp. 2972-2991, Aug. 2016. (SCI)

11. Ping-Yeh Yin, Chih-Wen Lu*, Yuan-Ho Chen, Hsin-Chin Liang, and Sheng-Pin Tseng “A 10-Bit Low-Power High-Color-Depth Column Driver with Two-Stage Multi-Channel RDACs for Small-Format TFT-LCD Driver ICs,” IEEE Journal of Display Technology, vol. 11, no. 12, pp. 1061-1068, Dec. 2015. (SCI)

12. Szi-Wen Chen* and Yuan-Ho Chen, “Hardware Design and Implementation of a Wavelet De-noising Procedure for Medical Signal Preprocessing,” Sensors, vol 15, pp. 26396-26414, 2015. (SCI)

13. Yuan-Ho Chen*, “Area-Efficient Fixed-Width Squarer with Dynamic Error-Compensation Circuit,” IEEE Trans. Circuits Syst. II., vol. 62, no. 9, pp. 851-855, Sep. 2015. (SCI)

14. Wen-Quan He, Yuan-Ho Chen*, and Shyh-Jye Jou, “High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation,” IEEE Trans. Circuits Syst. I. , vol. 62, no. 8, pp. 2052-2061, Aug. 2015. (SCI)

15. Yuan-Ho Chen* and Chieh-Yang Liu, “Area-efficient Video Transform for HEVC Applications,” Electron. Lett., vol. 51, no. 14, pp. 1065-1067, Jul, 2015. (SCI)

16. Yuan-Ho Chen*, “An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 1, pp. 203-207, Jan. 2015. (SCI)

17. Yuan-Ho Chen*, Ruei-Yuan Jou, Tsin-Yuan Chang, and Chih-Wen Lu, “A High-Throughput and Area-Efficient Video Transform Core with a Time Division Strategy,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 11, pp. 2268-2277, Nov. 2014. (SCI)

18. Yuan-Ho Chen* and Hsiao-Tzu Liu, “Hardware-Efficient Multi-Standard Video Transform Core,” J. Circuits Syst. Comput., vol. 23, no 8, 1450119, 2014. (SCI)

19. Yuan-Ho Chen*, “Low-cost fixed-width squarer by using a probability-compensated circuit,” Electron. Lett., vol. 50, no. 11, pp. 795-797, May 2014. (SCI)

20. Yuan-Ho Chen*, Chih-Wen Lu, Shian-Shing Shyu, Chung-Lin Lee, and Ting-Chia Ou, “A Multi-stage Fault-tolerant Multiplier with Triple Module Redundancy (TMR) Technique,” J. Circuits Syst. Comput., vol. 23, issue 5, 1450074, May 2014. (SCI)

21. Wen-Quan He, Yong-Ming Chang, and Yuan-Ho Chen*, “High-Throughput Rate FFT VLSI Implementation on Linear Array Based Design,” Journal of Advanced Engineering, vol. 9, no 2, pp. 87-92, Apr. 2014.

22. Yuan-Ho Chen*, Jyun-Neng Chen, Tsin-Yuan Chang, and Chih-Wen Lu, “A High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 3, pp. 463-474, Mar. 2014. (SCI)

23. Yuan-Ho Chen* and Tsin-Yuan Chang, “A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 4, pp. 655-664, Apr. 2012. (SCI)

24. Yuan-Ho Chen* and Tsin-Yuan Chang, “A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers,” IEEE Trans. Circuits Syst. I, vol. 59, no. 3, pp. 594-603, Mar. 2012. (SCI)

25. Chung-Yi Li*, Yuan-Ho Chen, Tsin-Yuan Chang, Lih-Yuan Deng, and Kiwing To, “Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 2, pp. 385-389, Feb. 2012. (SCI)

26. Yuan-Ho Chen*, Tsin-Yuan Chang, and Chung-Yi Li, “Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias,” IEEE J. Emerging Sel. Topics Circuits Syst., vol. 1, no. 3, pp. 277-288, Sep. 2011. (SCI)

27. Chung-Yi Li*, Yuan-Ho Chen, Tsin-Yuan Chang, and Jyun-Neng Chen, “A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications,” IEEE Trans. Circuits Syst. II, vol. 58, no. 4, pp. 215-219, Apr. 2011. (SCI)

28. Yuan-Ho Chen*, Tsin-Yuan Chang, and Chung-Yi Li, “High Throughput DA-based DCT with High Accuracy Error-Compensated Adder Tree,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 4, pp. 709-714, Apr. 2011. (SCI)

29. Bor-Sen Chen*, Bore-Kuen Lee, and Yuan-Ho Chen, “Power Control for CDMA Cellular Radio Systems via L1 Optimal Predictor,” IEEE Trans. Wireless Commun., vol. 5, no. 11, pp. 2914-2922, Oct. 2006. (SCI)

30. Bore-Kuen Lee, Yuan-Ho Chen, and Bor-Sen Chen*, “Robust H_inf Power Control for CDMA Cellular Communication Systems,” IEEE Trans. Signal Processing, vol. 54, no. 10, pp. 3947-3956, Oct. 2006. (SCI)

1. Yuan-Ho Chen*, “A Real-time Calibration Architecture with Dual Delay Line for the Implementation of FPGA-based TDC,” in Proc. IEEE ICASI,Tokyo/Japan, 2018.

2. Yuan-Ho Chen, Ming-Han Tsai, and Chih-Wen Lu*, “QRS Complex Detection Based On Wavelet Decomposition,” in Proc. IEEE ICASI, Sapporo/Japan, 2017.

3. Min-Xian Wei, Yu Juan, and Yuan-Ho Chen, “A VLSI implementation of Independent Component Analysis (ICA) for Biomedical Signal Separation,” inProc. IEEE ICASI, Sapporo/Japan, 2017.

4. Yu Juan, Min-Xian Wei, and Yuan-Ho Chen, “VLSI Implementation of the Integral Pulse Frequency Modulation Model for Heart Rate Variability System,” in Proc. IEEE ICASI, Sapporo/Japan, 2017.

5. Yuan-Ho Chen*, “A 50-ps FPGA-based TDC for Digital PET Applications,” in Proc. ACENS, Sapporo/Japan, 2017.

6. Yun-Hua Tseng, Yuan-Ho Chen*, and Chih-Wen Lu, “Cost-Effective Multi-standard Video Transform Core Using Time-distribution Scheme,” in Proc. IEEE ICCP, Taipei/Taiwan, 2016.

7. Yun-Hua Tseng, Yuan-Ho Chen*, and Chih-Wen Lu, "Cost-Effective Multi-Standard Video Transform Core Using Time-Sharing Architecture," in Proc. IEEE ISNE, Hsinchu/Taiwan, 2016.

8. Yuan-Ho Chen*, “A High Resolution FPGA-based Weighted Delay Line TDC with Nonlinearity Calibration,” in Proc. ACENS, Fukuoka/Japan, 2016, pp. 713-720.

9. Yi-Fan Ko, Chieh-Yang Liua, and Yuan-Ho Chen*, “A High Throughput Video Transform Architecture for High Efficiency Video Coding (HEVC) Applications,” in Proc. APCEAS, Osaks/Japan, 2015, pp. 450-455.

10. Chieh-Yang Liu, Wen-Quan He, Yung-Ming Chang, and Yuan-Ho Chen*, “Low-Cost Video Transform for HEVC,” in Proc. IEEE ICIST, Shenzhen/China, 2014, pp. 221-224. (EI)

11. Wen-Quan He, Chieh-Yang Liu, Wei-Yi Liu, and Yuan-Ho Chen*, “A High Accuracy Fixed-width Booth Multiplier Using Select Probability Estimation Bias,” in Proc. IEEE ICIST, Shenzhen/China, 2014, pp. 385-388. (EI)

12. Yuan-Ho Chen*, “A High Resolution FPGA-based Merged Delay Line TDC with Nonlinearity Calibration,” in Proc. IEEE ISCAS, Beijing/China, 2013, pp. 2432-2435. (EI)

13. Ping-Yeh Yin, Yuan-Ho Chen, Chih-Wen Lu*, Shian-Shing Shyu, Chung-Lin Lee, Ting-Chia Ou, and Yo-Sheng Lin, “A Multi-Stage Fault-Tolerant Multiplier with Triple Module Redundancy (TMR) Technique,” in Proc. IEEE ISMS, Bangkok /Thailand, 2013, pp. 636-641. (EI)

14. Jian-Shou Chen, Chih-Wen Lu*, Chin Hsia, and Yuan-Ho Chen, “A Low Noise Amplifier Employing Noise Canceling Technique for Ultrasound System Applications,” in Proc. IEEE IMSNA, Shenyang/China, 2012, pp. 35-38 (EI)

15. Yuan-Ho Chen, Chih-Wen Lu*, Tsin-Yuan Chang, and Chin Hsia, “A High Resolution FPGA-Based TDC with Nonlinearity Calibration,” in Proc. IEEE IMSNA, Shenyang/China, 2012, pp. 44-47 (EI)

16. Yuan-Ho Chen, Chih-Wen Lu*, Hsin-Chen Chiang, Tsin-Yuan Chang, and Chin Hsia, “A Low-Error Statistical Fixed-Width Multiplier and Its Applications,” in Proc. IEEE IMSNA, Shenyang/China, 2012, pp. 39-43. (EI)

17. Yuan-Ho Chen, Hsin-Chen Chiang, Tsin-Yuan Chang, Chih-Wen Lu*, and Pei-Yi Lai Li, “High Accuracy Fixed-width Booth Multipliers with Probabilistic Estimation Compensated Method,” in Proc. IEEE ICETEC, Three Gorges/China, 2012, pp. 1460-1463. (EI)

18. Yuan-Ho Chen*, Tsin-Yuan Chang, and Chih-Wen Lu, “A Low-Cost and High-Throughput Architecture for H.264/AVC Integer Transform by Using Four Computation Streams,” in Proc. IEEE ISIC, Singapore, 2011, pp. 380-383. (EI)

19. Yuan-Ho Chen*, Tsin-Yuan Chang, and Ruei-Yuan Jou, “A Statistical Error-Compensated Booth Multiplier and Its DCT Applications,” in Proc. IEEE Region 10 Conf. (TENCON), Fukuoka/Japan, 2010, pp. 1146-1149. (EI)

1. Yuan-Ho Chen, Chung-Yi Li and Lu-An Lai, “Fine-tuning accuracy using conditional probability of bottom sign-bit in Fixed-width Modified Booth Multiplier,” in Proc. VLSI Design/CAD Symposium, Taiwan, August 1-4, 2017.

2. Yun-Hua Tseng, Yuan-Ho Chen, and Chih-Wen Lu, “Adaptive Integrating Compressed Algorithm of CS and NPC for ECG Signal Compressed Algorithm,” in Proc. VLSI Design/CAD Symposium, Taiwan, August 1-4, 2017.

3. Min-Xian Wei, Yu Juan, Bing Jhe Chi, and Yuan-Ho Chen*, “VLSI implementation of Independent Component Analysis (ICA) for Biomedical Signal Separation,” in Proc. VLSI Design/CAD Symposium, Taiwan, August 1-4, 2017.

4. Wei-Ching Hsiao, Hsin- Han Chu, Chieh-Yang Liu, and Yuan-Ho Chen*, “Design of Automotive Electronics Based on FPGA” in Proc. Intelligent Automotive Electronics Workshop, Taoyuan, Dec. 2, 2014.

5. Wei-Yi Liu, Wen-Quan He, and Yuan-Ho Chen*, “High-accuracy and Area-efficiency Fixed-width Booth Multiplier” in Proc. Intelligent Automotive Electronics Workshop, Taoyuan, Dec. 2, 2014.

6. Chieh-Yang Liu, Yi-Fan Ko, and Yuan-Ho Chen*, “Low-cost Video Transform for High Efficiency Video Coding (HEVC) Applications,” in Proc. VLSI Design/CAD Symposium, Taichung, Taiwan, August 5-8, 2014.

7. Yong-Ming Chang, Wen-Quan He, and Yuan-Ho Chen*, “A Low-Cost FFT Processor for DVB-T Application” in Proc. Intelligent Automotive Electronics Workshop, Taoyuan, Dec. 10, 2013.

8. Wen-Ch’uan Ho, Yong-Ming Chang, and Yuan-Ho Chen*, “High-Throughput VLSI FFT Architecture With Systolic Array,” in Proc. 2013 VLSI Design/CAD Symposium, Kaohsiung, August 6-9, 2013.

9. Yuan-Ho Chen* and Tsin-Yuan Chang, “A Low-cost Architecture for High-throughput Multi-path Transform in Video Compression Applications,” in Proc. VLSI Design/CAD Symposium, Yunlin, August 2-5, 2011, pp. 25-28.

10. Ruei-Yuan Jou, Yuan-Ho Chen*, Tze-Yang Kao, and Tsin-Yuan Chang, “A High Performance Video Transform Engine by Using Simultaneous Forward and Inverse DCT,” in Proc. VLSI Design/CAD Symposium, Yunlin, Taiwan, August 2-5, 2011, pp. 572-575.

11. Hsin-Chen Chiang, Yuan-Ho Chen*, and Tsin-Yuan Chang, “Low-Error Fixed-Width Two’s-Complement Multipliers with Statistical Compensation Circuit,” in Proc. VLSI Design/CAD Symposium, Yunlin, Taiwan, August 2-5, 2011, pp. 29-32.

12. Yuan-Ho Chen* and Tsin-Yuan Chang, “High Performance DA-Based DCT with High Accuracy Error Compensated Adder Tree,” in Proc. VLSI Design/CAD Symposium, Hualien, Taiwan, August 4-7, 2009.