1.

C.-Y. Li, C.-L. Lee, M.-H. Hu, and H.-P. Chou, “A Fast Locking-in and Low Jitter PLL with a Process-Immune Locking-In Monitor”, IEEE Trans. On Very Large Scale Integration (VLSI) Systems, vol. 22, issue 10, pp. 2216 - 2220, 2014.

2.

C.-Y. Li, Y.-H. Chen, T.-Y. Chang, L.-Y. Deng, and K. W. To, “Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG,” IEEE Trans. On Very Large Scale Integration (VLSI) Systems, vol. 20, issue 2, pp. 385-389, 2012.

3.

C.-Y. Li, Y.-H. Chen, T.-Y. Chang, and J.-N. Chen, “A Probabilistic Estimation Bias Circuit for Fixed-width Booth Multiplier and Its DCT Applications,” IEEE Trans. on Circuits and Systems II: Express Brief, vol. 58, no. 4, pp. 215-219, Apr. 2011.

4.

Y.-H. Chen, C.-Y. Li, T.-Y. Chang, “Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 1, issue 3, pp. 277-288, 2011.

1.

C.-Y. Li, C.-W. Lu, H.-T. Chao, C. Hsia, “A 10-Bit Area-Efficient SAR ADC with Re-usable Capacitive Array,” Proc. of IEEE International Symposium on Anti-Counterfeiting, Security and Identification (ASID12), Accepted, Taiwan, Aug. 2012. (NSC 100-2628-E-260-002).

2.

C.-Y. Li, H.-P. Chou, L.-Y. Deng, J.-J. Horng Shiau, H. H.-S. Lu, “Non-linear Pseudo-Random Number Generators via Coupling DX Generators with the Logistic Map,” Proc. of IEEE International Symposium on Anti -Counterfeiting, Security and Identification (ASID12), Accepted, Taiwan, Aug. 2012. (NSC 101-B-000-8K8, 101-2118-M-009-005-MY2, 99-2118-M-009-003-MY2, and 98-2118-M-009-004-MY3).

3.

C.-Y. Li and T.-Y. Chang, “InvMixColumn Byte-level Decomposition using Greedy Algorithm and Design of AES,” Proc. of International Congress on Computer Applications and Computational Science (CACS10), pp. 1047-1050, Singapore, Dec. 2010. (NSC 98-2221-E-007-095，NSC 99-2221-E-007-119).

4.

C.-Y. Li, T.-Y. Chang, and C. C. Huang, “A Nonlinear PRNG Using Digitized Logistic Map with Self-Reseeding Method,” Proc. of IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT10), pp. 108-111, Taiwan, Apr. 2010. (NSC 98-2221-E-007-095).

5.

C.-Y. Li, C.-F. Chien, J.-H. Hong and T.-Y. Chang, “An Efficient Area-Delay Product Design for MixColumns / InvMixColumns in AES,” Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI08), pp. 503-506, France, Apr. 2008. (NSC 94-2220-E-390-002, NSC 94-2220-E-007-027).

6.

C.-Y. Li, C.-Y. Chou, and T.-Y. Chang, “A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency Range,” Proc. of IEEE Asian Test Symposium (ATS06), pp. 313-317, Fukouka, Japan, Nov. 2006. (NSC 94-2220-E-007-004, NSC 94-2220-E-007-029).

7.

C.-Y. Li, J.-S. Chen, and T.-Y. Chang, “A Chaos-Based Pseudo Random Number Generator Using Timing-Based Reseeding Method,” Proc. of IEEE International Symposium on Circuits and Systems (ISCAS06) 2006, pp. 3277-3280, Greece. (NSC 94-2220-E007-029, MoEA 93-EC-17-A-03-S1-0002) (EI).

8.

J.-S. Chen, C.-Y. Li, and T.-Y. Chang, “The Reseeding Timing for a 32-bit Digital Chaos-Based Pseudo Random Number Generator,” Proc. of WRTLT05, pp. 131-134, Harbin, China, July, 2005. (NSC 93-2220-E-007-029, MoEA 93-EC-17-A-03-S1-0002).

9.

T.-Y. Chang, C.-Y. Li, and M.-H. Hu, “An Robust Time-to-Voltage Converter for PLL Jitter Measurement,” Informal digest of 1st VLSI Test Technology Workshop, pp. P2.4, Hsinchu, Taiwan, July, 2007. (NSC 95-2220-E-007-011 and NSC 95-2220-E-007-039).

1.

C.-Y. Li, T.-Y. Chang, and J.-R. Huang, “High-speed parity generation device for binary addition,” Taiwan Patent, no. New-Type 177100, patent term beginning on June 23, 2001 and ending on October 1, 2010.