Journal articles & book chapters : :
J1. Yuan-Ho Chen*, “An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 1, pp. 203-207, Jan. 2015. (SCI)
J2. Yuan-Ho Chen*, Ruei-Yuan Jou, Tsin-Yuan Chang, and Chih-Wen Lu, “A High-Throughput and Area-Efficient Video Transform Core with a Time Division Strategy,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 11, pp. 2268-2277, Nov. 2014. (SCI)
J3. Yuan-Ho Chen* and Hsiao-Tzu Liu, “Hardware-Efficient Multi-Standard Video Transform Core,” J. Circuits Syst. Comput., vol. 23, no 8, 1450119, 2014. (SCI)
J4. Yuan-Ho Chen*, “Low-cost fixed-width squarer by using a probability-compensated circuit,” Electron. Lett., vol. 50, no. 11, pp. 795-797, May 2014. (SCI)
J5. Yuan-Ho Chen*, Chih-Wen Lu, Shian-Shing Shyu, Chung-Lin Lee, and Ting-Chia Ou, “A Multi-stage Fault-tolerant Multiplier with Triple Module Redundancy (TMR) Technique,” J. Circuits Syst. Comput., vol. 23, no 5, 1450074, 2014. (SCI)
J6. Wen-Quan He, Yong-Ming Chang, and Yuan-Ho Chen*, “High-Throughput Rate FFT VLSI Implementation on Linear Array Based Design,” Journal of Advanced Engineering, vol. 9, no 2, pp. 87-92, Apr. 2014.
J7. Yuan-Ho Chen*, Jyun-Neng Chen, Tsin-Yuan Chang, and Chih-Wen Lu, “High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 3, pp. 463-474, Mar. 2014. (SCI)
J8. Yuan-Ho Chen* and Tsin-Yuan Chang, “A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 4, pp. 655-664, Apr. 2012. (SCI)
J9. Yuan-Ho Chen* and Tsin-Yuan Chang, “A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers,” IEEE Trans. Circuits Syst. I, vol. 59, no. 3, pp. 594-603, Mar. 2012. (SCI)
J10. Chung-Yi Li*, Yuan-Ho Chen, Tsin-Yuan Chang, Lih-Yuan Deng, and Kiwing To, “Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 2, pp. 385-389, Feb. 2012. (SCI)
J11. Yuan-Ho Chen*, Tsin-Yuan Chang, and Chung-Yi Li, “Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias,” IEEE J. Emerging Sel. Topics Circuits Syst., vol. 1, no. 3, pp. 277-288, Sep. 2011. (SCI)
J12. Chung-Yi Li*, Yuan-Ho Chen, Tsin-Yuan Chang, and Jyun-Neng Chen, “A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications,” IEEE Trans. Circuits Syst. II, vol. 58, no. 4, pp. 215-219, Apr. 2011. (SCI)
J13. Yuan-Ho Chen*, Tsin-Yuan Chang, and Chung-Yi Li, “High Throughput DA-based DCT with High Accuracy Error-Compensated Adder Tree,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 4, pp. 709-714, Apr. 2011. (SCI)
J14. Bor-Sen Chen*, Bore-Kuen Lee, and Yuan-Ho Chen, “Power Control for CDMA Cellular Radio Systems via Optimal Predictor,” IEEE Trans. Wireless Commun., vol. 5, no. 11, pp. 2914-2922, Oct. 2006. (SCI)
J15. Bore-Kuen Lee, Yuan-Ho Chen, and Bor-Sen Chen*, “Robust Power Control for CDMA Cellular Communication Systems,” IEEE Trans. Signal Processing, vol. 54, no. 10, pp. 3947-3956, Oct. 2006. (SCI)
Conference papers : :
C1. Chieh-Yang Liu, Wen-Quan He, Yung-Ming Chang, and Yuan-Ho Chen*, “Low-Cost Video Transform for HEVC,” in Proc. IEEE ICIST, Shenzhen/China, 2014, pp. 221-224. (EI)
C2. Wen-Quan He, Chieh-Yang Liu, Wei-Yi Liu, and Yuan-Ho Chen*, “A High Accuracy Fixed-width Booth Multiplier Using Select Probability Estimation Bias,” in Proc. IEEE ICIST, Shenzhen/China, 2014, pp. 385-388. (EI)
C3. Yuan-Ho Chen*, “A High Resolution FPGA-based Merged Delay Line TDC with Nonlinearity Calibration,” in Proc. IEEE ISCAS, Beijing/China, 2013, pp. 2432-2435. (EI)
C4. Ping-Yeh Yin, Yuan-Ho Chen, Chih-Wen Lu*, Shian-Shing Shyu, Chung-Lin Lee, Ting-Chia Ou, and Yo-Sheng Lin, “A Multi-Stage Fault-Tolerant Multiplier with Triple Module Redundancy (TMR) Technique,” in Proc. IEEE ISMS, Bangkok /Thailand, 2013, pp. 636-641. (EI, Cite=1/1, 1)
C5. Jian-Shou Chen, Chih-Wen Lu*, Chin Hsia, and Yuan-Ho Chen, “A Low Noise Amplifier Employing Noise Canceling Technique for Ultrasound System Applications,” in Proc. IEEE IMSNA, Shenyang/China, 2012, pp. 35-38 (EI)
C6. Yuan-Ho Chen, Chih-Wen Lu*, Tsin-Yuan Chang, and Chin Hsia, “A High Resolution FPGA-Based TDC with Nonlinearity Calibration,” in Proc. IEEE IMSNA, Shenyang/China, 2012, pp. 44-47 (EI)
C7. Yuan-Ho Chen, Chih-Wen Lu*, Hsin-Chen Chiang, Tsin-Yuan Chang, and Chin Hsia, “A Low-Error Statistical Fixed-Width Multiplier and Its Applications,” in Proc. IEEE IMSNA, Shenyang/China, 2012, pp. 39-43. (EI)
C8. Yuan-Ho Chen, Hsin-Chen Chiang, Tsin-Yuan Chang, Chih-Wen Lu*, and Pei-Yi Lai Li, “High Accuracy Fixed-width Booth Multipliers with Probabilistic Estimation Compensated Method,” in Proc. IEEE ICETEC, Three Gorges/China, 2012, pp. 1460-1463. (EI)
C9. Yuan-Ho Chen*, Tsin-Yuan Chang, and Chih-Wen Lu, “A Low-Cost and High-Throughput Architecture for H.264/AVC Integer Transform by Using Four Computation Streams,” in Proc. IEEE ISIC, Singapore, 2011, pp. 380-383. (EI, Cite=3/0, 3)
C10. Yuan-Ho Chen*, Tsin-Yuan Chang, and Ruei-Yuan Jou, “A Statistical Error-Compensated Booth Multiplier and Its DCT Applications,” in Proc. IEEE Region 10 Conf. (TENCON), Fukuoka/Japan, 2010, pp. 1146-1149. (EI, Cite=7/3, 7)