C. Y. Li, Y. H. Chen, L. A. Lai, W. C. Yeh, J. Yang, “Simple and Hardware-efficient Row-based Direct-Mapping Estimators in Fixed-width Modified Booth Multipliers,” International Journal of Circuit Theory and Applications, 2021. DOI: 10.1002/cta.2937. (IF: 1.581, Rank: 174/266(Q3), ENGINEERING, ELECTRICAL & ELECTRONIC - SCIE)
C.-W. Su, H. Jin, C.-Y. Li, Y.-J. Liao, K.-S. Chin, "Pattern-Reconfigurable Dual-Band Dipole Antenna Array with Four Switchable Beams for Full Coverage in Horizontal Plane" IET Microwaves, Antennas & Propagation, vol. 15, issue 1, pp. 21-32, JANUARY 2021. (IF: 2.036, Rank: 139/266(Q3), ENGINEERING, ELECTRICAL & ELECTRONIC - SCIE)
Y.-L. Hsieh, L.-B. Chang*, M.-J. Jeng, C.-Y. Li, C.-F. Shih, H.-T. Wang, Z.-X. Ding, C.-N. Chang, H.-Z. Lo and Y.-P. Chiang, "Annealing-Dependent Breakdown Voltage and Capacitance of Gallium Oxide-Based Gallium Nitride MOSOM Varactors," Materials. vol. 13, issue. 21, pp. 1-16, JANUARY/FEBRUARY 2020. (IF: 3.057, Rank: 132/314(Q2), MATERIALS SCIENCE, MULTIDISCIPLINARY -- SCIE)
C.-Y. Li, T.-H. Chen and H.-C. Chen, "A Simple Control Strategy Extending Intrinsic Current Balancing Characteristics to Achieve a Full Operating Range for Interleaved Voltage-Doubler Boost DC-DC Converters," IEEE Transactions on Industry Applications. vol. 56, no. 1, pp. 436-445, JANUARY/FEBRUARY 2020. (IF: 3.347, Rank: 76/266(Q2), ENGINEERING, ELECTRICAL & ELECTRONIC - SCIE)
C.-Y. Li, N.-C. Chao and H.-C. Chen “Design and Implementation of Four-Switch Current Sensorless Control for Three-Phase PFC Converter,” IEEE Transactions on Industrial Electronics, vol. 67, no. 4, pp. 3307-3312, April 2020. (IF: 7.503, Rank: 1/61(Q1), INSTRUMENTS & INSTRUMENTATION - SCIE)
H.-J. Lee, Eric S. Li, C.-Y. Li, Y.-Y. Lin, Roger Lu and K.-S. Chin, “Bandwidth and Gain Enhancement of LTCC 60-GHz Patch Antenna by Using AMC Structure,” Journal of Electromagnetic Waves and Applications, vol. 33, issue. 11, pp. 1463-1476, 2019. (IF: 1.351, Rank: 188/266(Q3), ENGINEERING, ELECTRICAL & ELECTRONIC - SCIE)
C.-M. Tan, U. Narula, L.A. Lai, S. Pandey, J.-H. Tung, C.-Y. Li, “Optimal maintenance strategy on medical instruments used for haemodialysis process,” Eksploatacja i Niezawodnosc – Maintenance and Reliability, vol. 21, no. 2, 318–328, 2019. (IF: 1.383, Rank: 37/86(Q2), ENGINEERING, MULTIDISCIPLINARY - SCIE)
H.-J. Lee, Eric S. Li, H.-Y. Jin, C.-Y. Li, K.-S. Chin*, “60-GHz wideband LTCC microstrip patch antenna array with parasitic surrounding stacked patches,” IET Microwaves, Antennas & Propagation, vol. 13, issue. 1, pp. 35-41, 2019. (IF: 2.036, Rank: 139/266(Q3), ENGINEERING, ELECTRICAL & ELECTRONIC - SCIE)
Y.-H. Chen, C.-Y. Li (*), L.-A. Lai, “Fine-tuning accuracy using conditional probability of the bottom sign-bit in Fixed-width Modified Booth Multiplier”, Circuits, Systems and Signal Processing (CSSP), vol. 37, no. 7, pp. 3115--3130, 2018. (IF: 1.922, Rank: 147/266(Q3), ENGINEERING, ELECTRICAL&ELECTRONIC- SCIE)
C.-Y. Li and L.-Y. Deng, “A Class of Hardware-based PRNGs with Maximum Periods”, Journal of the Chinese Statistical Association, vol. 55, pp. 145–159, 2017.
C.-Y. Li and B.-X. Wu, “Zeroing of Power Supply Noise Sensitivity for Ring Oscillators Operating from 1 to 4 GHz”, Microelectronics Journal, vol. 67, issue 9, pp. 128 - 134, 2017. (IF: 1.284, Rank: 194/266(Q3), ENGINEERING, ELECTRICAL & ELECTRONIC - SCIE)
A. P. S. Isabel, C.-H. Kao, R. K. Mahanty, Y.-C. Sermon Wu, C.-Y. Li, C.-Y. Lin, and C.-F. Lin, “Sensing and structural properties of Ti-doped tin oxide (SnO2) membrane for bio-sensor applications”, Ceramics International, vol. 43, issue 13, pp. 10386 - 10391, 2017. (IF: 3.450, Rank: 2/28(Q1), MATERIALS SCIENCE, CERAMICS - SCIE)
C.-Y. Li, C.-L. Lee, M.-H. Hu, and H.-P. Chou, “A Fast Locking-in and Low Jitter PLL with a Process-Immune Locking-In Monitor”, IEEE Trans. On Very Large Scale Integration (VLSI) Systems, vol. 22, issue 10, pp. 2216 - 2220, 2014. 2216 - 2220, 2014 (IF: 1.946, Rank:26/53(Q2), COMPUTER SCIENCE, HARDWARE & ARCHITECTURE - SCIE)
C.-Y. Li, Y.-H. Chen, T.-Y. Chang, L.-Y. Deng, and K. W. To, “Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG,” IEEE Trans. On Very Large Scale Integration (VLSI) Systems, vol. 20, issue 2, pp. 385-389, 2012.
C.-Y. Li, Y.-H. Chen, T.-Y. Chang, and J.-N. Chen, “A Probabilistic Estimation Bias Circuit for Fixed-width Booth Multiplier and Its DCT Applications,” IEEE Trans. on Circuits and Systems II: Express Brief, vol. 58, no. 4, pp. 215-219, Apr. 2011.
Y.-H. Chen, C.-Y. Li, T.-Y. Chang, “Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 1, issue 3, pp. 277-288, 2011.
Y.-H. Chen, T.-Y. Chang, C.-Y. Li, “High Throughput DA-based DCT with High Accuracy Error-compensated Adder Tree,” IEEE Trans. On Very Large Scale Integration (VLSI) Systems, vol. 19, no. 4, pp. 709-714, Apr. 2011.
☀ Conference
Chung-Yi Li, Tzu-Yu Chen, Chin Hsia, Deng-fong Lu, Yue-Liang Chou and *Hung-Chi Chen, and Shinn-Yn Lin, “Robust Cascaded Boost Converter with See-Saw Stress-Relief Control,” IEEE The 20th International SoC Conference (ISOCC 2023), Jiju, Korea, October, 25-27, 2023.
Chin Hsia, Chung-Yi Li, Deng-Fong Lu, and Tzu-Yu Chen, “Integrated All-GaN Driver for High-voltage DC-DC Power Converters,” IEEE The 20th International SoC Conference (ISOCC 2023), Jiju, Korea, October, 25-27, 2023.
C. -Y. Li, C. -F. Nien, L. Lin and H. -C. Chen, "A Generalized Current Balancing Control for Series-Capacitor Buck Converter with Interleaved Phase Angle," 2023 IEEE 24th Workshop on Control and Modeling for Power Electronics (COMPEL), Ann Arbor, MI, USA, 2023, pp. 1-5, doi: 10.1109/COMPEL52896.2023.10221016.
L.-A. Lai, L.-J. Lai, C.-Y. Li, H.-C. Chen, “Hardware-efficient evolutionary compensation circuit for fixed-width Booth multiplier,” in VLSI Design/CAD Symposium, Taiwan, August 3-6, 2021.
L.-A. Lai, L.-J. Lai, C.-Y. Li, and Y.-J. Liao, “Potentials of Evolutionary Compensation Circuit Design in Fixed-Width Booth Multiplier using Genetic Algorithm,” International Electron Devices & Materials Symposium 2020, Oct. 15-16, 2020, Best paper award.
Che-Yu Lu, Hung-Chi Chen* and Chung-Yi Li, “Symmetrical Voltage Balancing Control for Four-level Flying Capacitor Converter Based on Phase-Shifted PWM,” Proc. of IEEE International Power Electronics Conference (IEEE APEC 2019) , pp.1 -5, Anaheim, USA, Mar., 2019.
Hung-Chi Chen, Tien-Hung Chen, and Chung-Yi Li, “Modeling and Control for Interleaved Voltage-Doubler Boost Converter,” Proc. of IEEE Energy Conversion Congress and Exposition (IEEE ECCE 2018) , pp.1 -5, Oregon, USA, Sep., 2018.
M. Gao, N. D’Ascenzo, C.-M. Kao, Y. Hua , X. Lyu , I.-T. Hsiao, C.-Y. Li, H.-H. Chen, J.-H. Hong, T.-C. Yen, Q. Xie, “Measurement of Proton Beam Generated β+ Radioactivity by Use of All-digital PET Detectors,” Proc. of IEEE Nuclear Science Symposium and Medical Imaging Conference (IEEE NSSMIC 2017), Georgia, USA, Oct., 2017.
Hung-Chi Chen, Zhi-Xuan Wu, and Chung-Yi Li, “Average Current Method to Detect Open‐Winding Fault of Three‐Phase Permanent Magnet Synchronous Motors, ” Proc. of IEEE European Conference on Power Electronics and Applications (IEEE EPE 2016), Karlsruhe, Germany, Sep., 2016. (MOST 105-2221-E-182-076-)
Daoming Xi, Yuqing Liu, Chien-Min Kao, Xiaoqing Cao, Rong Yuan, Chung-Yi Li, Xiao Liang, Jun Zhu, Luyao Wang, Zhenzhou Deng, Heejong Kim, Peng Xiao, Qingguo Xie, “Trans-PET: Towards Plug and Imaging Coincidence Measurement,” Proc. of IEEE Nuclear Science Symposium and Medical Imaging Conference (NSSMIC 2015), San Diego, USA, Nov., 2015. (MOST 103-2221-E-182-072-)
Che-Yu Lu, Hung-Chi Chen, Wei-Cheng Chen, and Chung-Yi Li, “Current Sensorless Control for Dual-Boost Half-Bridge PFC Converter,” Proc. of IEEE Energy Conversion Congress and Exposition (IEEE ECCE 2015) , pp. 669-675, Montreal, Canada, Oct., 2015.
Chih-Ming Huang, Liang-Chun Wang, Chung-Yi Li and Lih-Yuan Deng, “A Class of Hardware-efficient PRNGs with Maximum Periods,” Proc. of IEEE Global High Tech Congress on Electronics (GHTCE 2014), ShenZhen, China, Nov., 2014. (MOST 102-2218-E-182-005)
C.-Y. Li, C.-W. Lu, H.-T. Chao, C. Hsia, “A 10-Bit Area-Efficient SAR ADC with Re-usable Capacitive Array,” Proc. of IEEE International Symposium on Anti-Counterfeiting, Security and Identification (ASID12), Accepted, Taiwan, Aug. 2012. (NSC 100-2628-E-260-002)
C.-Y. Li, H.-P. Chou, L.-Y. Deng, J.-J. Horng Shiau, H. H.-S. Lu, “Non-linear Pseudo-Random Number Generators via Coupling DX Generators with the Logistic Map,” Proc. of IEEE International Symposium on Anti -Counterfeiting, Security and Identification (ASID12), Accepted, Taiwan, Aug. 2012. (NSC 101-B-000-8K8, 101-2118-M-009-005-MY2, 99-2118-M-009-003-MY2, and 98-2118-M-009-004-MY3)
C.-Y. Li and T.-Y. Chang, “InvMixColumn Byte-level Decomposition using Greedy Algorithm and Design of AES,” Proc. of International Congress on Computer Applications and Computational Science (CACS10), pp. 1047-1050, Singapore, Dec. 2010. (NSC 98-2221-E-007-095, NSC 99-2221-E-007-119)
C.-Y. Li, T.-Y. Chang, and C. C. Huang, “A Nonlinear PRNG Using Digitized Logistic Map with Self-Reseeding Method,” Proc. of IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT10), pp. 108-111, Taiwan, Apr. 2010. (NSC 98-2221-E-007-095)
C.-Y. Li, C.-F. Chien, J.-H. Hong and T.-Y. Chang, “An Efficient Area-Delay Product Design for MixColumns / InvMixColumns in AES,” Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI08), pp. 503-506, France, Apr. 2008. (NSC 94-2220-E-390-002, NSC 94-2220-E-007-027)
C.-Y. Li, C.-Y. Chou, and T.-Y. Chang, “A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency Range,” Proc. of IEEE Asian Test Symposium (ATS06), pp. 313-317, Fukouka, Japan, Nov. 2006. (NSC 94-2220-E-007-004, NSC 94-2220-E-007-029)
C.-Y. Li, J.-S. Chen, and T.-Y. Chang, “A Chaos-Based Pseudo Random Number Generator Using Timing-Based Reseeding Method,” Proc. of IEEE International Symposium on Circuits and Systems (ISCAS06) 2006, pp. 3277-3280, Greece. (NSC 94-2220-E007-029, MoEA 93-EC-17-A-03-S1-0002) (EI)
J.-S. Chen, C.-Y. Li, and T.-Y. Chang, “The Reseeding Timing for a 32-bit Digital Chaos-Based Pseudo Random Number Generator,” Proc. of WRTLT05, pp. 131-134, Harbin, China, July, 2005. (NSC 93-2220-E-007-029, MoEA 93-EC-17-A-03-S1-0002)
T.-Y. Chang, C.-Y. Li, and M.-H. Hu, “An Robust Time-to-Voltage Converter for PLL Jitter Measurement,” Informal digest of 1st VLSI Test Technology Workshop, pp. P2.4, Hsinchu, Taiwan, July, 2007. (NSC 95-2220-E-007-011 and NSC 95-2220-E-007-039)
C.-Y. Li, C.-F. Chien, and T.-Y. Chang, “High Speed and Low Cost Implementations in Mix-Column/InvMix-Column,” Informal digest of VLSI/CAD Symp., pp. 620-623, Hualian Taiwan, Aug. 2007. (NSC 95-2220-E-007-011)
C.-H. Lin, C.-Y. Li and T.-Y. Chang, “High Fault Coverage Built-In Self-Test for Phase-Locked Loops,” Informal digest of VLSI/CAD Symp., pp. P22, Hualian, Taiwan, Aug. 2006. (NSC 94-2220-E007-004 and 94-2220-E007-029)
C.-C. Lee, S.-S. Yang, C.-Y. Li, and T.-Y. Chang, “Built-In Self-Measurement for SRAM Sense Amplifier Input Signal,” Proc. of VLSI/CAD Symp., pp. P1-11, Hualian, Taiwan, Aug. 2005. (NSC 93-2220-E-007-004)
H.-H. Chiu, P.-L. Chen, C.-Y. Li, and T.-Y. Chang, “A Delay Test Wrapper Design on Core-Based System-on-Chip,” Informal digest of VLSI/CAD Symp., pp. P2-62, Hualian, Taiwan, Aug. 2005. (MoEA 93-EC-17-A-03-S1-0002)
C.-Y. Li, T.-Y. Chang, and J.-R. Huang, “High-speed parity generation device for binary addition,” Taiwan Patent, no. New-Type 177100, patent term beginning on June 23, 2001 and ending on October 1, 2010.
