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長庚大學 電子工程學系
勤勞樸實 追求卓越
分類清單
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高泉豪教授

高泉豪

教授

組別

積體電路製程

電話

5783

Email

chkao[at]mail.cgu.edu.tw ([at]=@)

實驗室

薄膜奈米製程實驗室(工學院8樓E0809)

學歷

u  交通大學電子工程博士

u  成功大學電機工程碩士 

經歷

u  長庚大學副教授 ( 2008 -  )

u  長庚大學助理教授(2005-2008)

u  矽成積體電路公司(ISSI)技術開發處經理

u  臺湾積體電路公司(TSMC)研發部門工程師 

開授課程

98學年度第二學期

 

專長與研究領域

  1. (I)                  高介電(High-K)絕緣層製作
  2. (II)                TFT薄膜電晶體元件製程
  3. (III)              奈米元件製程
  4. (IV)              生醫感測元件製程

簡歷

Kao, Chyuan-Haur  received his M.S., and Ph.D. degrees in Electronic Engineering from National Cheng Kung University(NCKU), and National Chiao Tung University(NCTU), Taiwan, Republic of China, in 1991, and 1998, respectively.      In 2005, he joined the Department of Electronic Engineering at Chang Gung University, Tao-Yuan, Taiwan, as an Assistant Professor, and became an Associate Professor in 2008. His current research interests focus on thin film transistor (TFT) process technology and nano-device fabrication including high-k dielectrics, flash memory nano-device, and biosensors, etc.

 

著作列表

Journal articles:

  1. Chyuan-Haur Kao, Hsiang Chen, Yu Tsung Pan, Jing Sing Chiu, Tien-Chang Lu “The Characteristics of the High-K Er2O3 (Erbium Oxide) Deposited on Polycrystalline Silicon,” submitted to Journal of Applied Physics.
  2. Chyuan-Haur Kao, Hsiang Chen, C. S. Chuang, C. C. Chen,” The TiO2 (Titanium Oxide) Charge Trapping Layer for Nonvolatile Memory Applications,” submitted to Applied Surface Science.
  3. Chyuan-Haur Kao, Hsiang Chen, Yu Tsung Pan, Jing Sing Chiu, Shih Po Lin
  4. Chao Sung Lai, “The Investigation of the High-K Gd2O3 (Gadolinium Oxide) Inter-Dielectrics Deposited on the Polycrystalline Silicon, Journal of Electrochemical Society, Vol. 157, No. 9, 2010. 【SCI=2.437】
  5. Chyuan Haur Kao*, C. S. Lai, W. H. Sung, and C. H. Lee,“ The Characteristics of Fluorinated Polycrystalline Silicon Oxides and Thin Film Transistors by CF4 Plasma Treatment,” Thin Solid Films, will be accepted for publication, 2010. 【SCI=1.884】
  6. Chyuan-Haur Kao*, Hsiang Chen, Jing Sing Chiu, and Kung Shao Chen, Physical and Electrical Characteristics of the High-K Ta2O5 (Tantalum Pentoxide) Dielectric Deposited on the Polycrystalline Silicon,” Applied Physics Letter, Vol. 96, 112901, 2010. 【SCI=3.726】
  7.  Chyuan-Haur Kao*, T. C. Chan, Kung Shao Chen, Yu-Teng Chung, and Wen-Shih Luo,” Physical and Electrical Characteristics of the High-K Nd2O3 Polyoxide Deposited on Polycrystalline silicon,” Microelectronics Reliability, Vol. 50, p. 709-712, 2010. 【SCI=1.29】
  8. Chyuan Haur Kao*, K. S. Chen, J. S. Chiu, C. S. Chan, T. C. Chen, W. S. Luo, and Y. T. Chung, “High-K Ta2O5 Polyoxide Deposited on Polycrystalline with NH3 Plasma Treatment”, Electrochemical Society (ECS) Transactions, vol. 19, issue. 4, p. 335-340, May, 2009. 【EI】
  9. Tse-Heng Chou, Yean-Kuen Fang, Yen-Ting Chiang,Kung-Cheng Lin,Cheng-I Lin, Chyuan-Haur Kao, and Hsiao-Yi Lin,”The Pd/TiO2/n-LTPS Thin-Film Schottky Diode on Glass Substrate for Hydrogen SensingApplications,“ IEEE Electron Device Lett., vol. 29, no.11, p. 1232-1235, Nov. 2008. 【SCI=3.049】
  10. Chyuan Haur Kao*, C. S. Lai, C. S. Huang, and K. M. Fan, “Ge-Nanocrystal Charge Trapping Devices Fabricated by One-Step Oxidation on Poly-SiGe”, Applied Surface Science, Vol. 255, p.2512-2516, 2008. 【SCI=1.576】
  11.  Chyuan Haur Kao*, W.H. Sung, ”Negative Bias Temperature Instability for P-channel of LTPS Thin Film Transistors with Fluorine Implantation”, Mater. Res. Soc. Symp. Proc. Vol. 1066, A06-21, p.1-5, 2008. 【EI】
  12. Chyuan Haur Kao*, C. S. Lai, M. C. Tsai, C. H. Lee, C. S. Huang, and C. R. Chen, “Using Thermal Oxidation and Rapid Thermal Annealing on Polycrystalline-SiGe for Ge nanocrystal,” Mater. Res. Soc. Symp. Proc. Vol. 1071, F03-21, p.1-6, 2008. 【EI】
  13.  Chyuan Haur Kao*, C. S. Chen, C. H. Lee,” Charge-trapping properties of poly-silicon oxides by rapid thermal N2O process”, Microelectronics Journal, Vol. 39, p. 1075-1079, 2008. 【SCI=0.859】
  14.  J.C. Liao, Y.K. Fang, C. H. Kao and C.Y.Cheng,” Dynamic Negative Bias Temperature Instability (NBTI) of Low-Temperature Polycrystalline Silicon (LTPS) Thin Film Transistors,“ IEEE Electron Device Lett., vol. 29, no.5, p. 477-479, May. 2008. 【SCI=3.049】
  15.  Chyuan Haur Kao*, Chao Sung Lai , M. C. Tsai , K. M. Fan, C. H. Lee, “ SiGe Nanocrystals Fabricated by One-Step Thermal Oxidation and Rapid Thermal Annealing,Electrochemical Solid State Letter, Vol. 11, No. 4, p. 44-46, 2008. 【SCI=2.001】
  16. Chyuan Haur Kao*, and C. S. Lai,” Thin-Film Transistors using TEOS Gate Dielectrics with RTN2O Annealing,Semiconductor Science Technology, Vol. 23, 025020, p.1-6, 2008. 【SCI=1.434】
  17. Chyuan Haur Kao*, W.H. Sung, and C.S. Chen,” Investigation of the doping and thickness effects of polysilicon oxide by rapid thermal N2O oxidation,” Microelectronic Engineering, Vol. 85, p. 408-413, 2008. 【SCI=1.583】
  18. C. S. Lai, Chyuan Haur Kao*, and C. L. Lee, Tan Fu Lei, “Nitrogen Effects on the Integrity of Silicon Dioxide Grown on Polycrystalline Silicon,” Journal of Electrochemical Society, Vol. 154. No. 10, p.883-886, 2007. 【SCI=2.437】
  19. Chyuan Haur Kao*, C. S. Lai and C. L. Lee,” Electrical and Reliability Improvement in Polyoxide by Fluorine Implantation,Journal of Electrochemical Society, Vol. 154. No. 4, p.259-262, 2007. 【SCI=2.437】
  20. Chyuan Haur Kao*, C. S. Lai and C. L. Lee,”Polarity asymmetry of Polyoxide Grown on Phosphorus in-situ Doped Polysilicon,“ Journal of Electrochemical Society, Vol. 153, No. 9, p. 860-865, 2006. 【SCI=2.437】
  21. Chyuan Haur Kao*, C. S. Lai and C. L. Lee,” Oxide Grown on Polycrystal-silicon by Rapid Thermal Oxidation in N2O,“ Journal of Electrochemical Society, Vol. 153, No. 2, p. 128-133, 2006.【SCI=2.437】

Conference & proceeding papers:

  1. Chyuan. Haur. Kao, Hsiang Chen, Jing-Siang Chiu, Yu-Teng Chung, Hsuan-Chi Fan, Pan-Yu Tsung, Yu-Cheng Liao, Wen-Shih Luo, Pei-Lun Lai, Chuan-You Huang,” Physical and Electrical Characteristics of the High-K Er2O3 Polyoxide Deposited on Polycrystalline silicon,” 2010 China Semiconductor Technology International Converence (CSTIC), Shanghai, China.
  2. Chyuan-Haur Kao, Kung Shao Chen, Yu-Teng Chung,” The Hot-Carrier- induced Degradation and Positive/Negative Bias Temperature Instability in 65 nm CMOSFET Devices,” 2010 China Semiconductor Technology International Converence (CSTIC), Shanghai, China.
  3. Chuang Chih Sheng, Chyuan Haur Kao, Hsiang Chen, Chun Chi Chen, Kung Shao Chen, Lin Shih Po, Ching Hua Huang, Shih Nan Cheng, Tz Ying Li, Kai-shiang Ho, Jiun-cheng Ou, Chau-shian Lin,” The Characterization of TiO2 Titanium Oxide Trapping Layer memories,” 2009 International Electron Devices and Materials Symposium (IEDMS), Taoyuan, Taiwan, R.O.C.
  4. T. C. Chan, Chyuan. Haur. Kao, Wen-Shih Luo, Kung Shao Chen, Pan-Yu Tsung, Yu-Cheng Liao, Yu-Teng Chung, Fan-Hsuan Chi, Pei-Lun Lai, Chuan-You Huang,” Physical and Electrical Characteristics of the High-K Nd2O3 Polyoxide Deposited on Polycrystalline silicon,” 2009 International Electron Devices and Materials Symposium (IEDMS), Taoyuan, Taiwan, R.O.C.
  5. Jing-Siang Chiu, Chyuan. Haur. Kao, Hsiang Chen, Fan-Hsuan Chi, Pan-Yu Tsung, Yu-Cheng Liao, Yu-Teng Chung, Wen-Shih Luo, Pei-Lun Lai, Chuan-You Huang,” The Characteristics of the High-K Er2O3 (Erbium) Polysilicon Oxide,” 2009 International Electron Devices and Materials Symposium (IEDMS), Taoyuan, Taiwan, R.O.C.
  6. K. S. Chen, Chyuan-Haur Kao, T. C. Chan, S. P. Lin, S. Y. Chen,“ The Hot-Carrier-induced Degradation and Positive/Negative Bias  Temperature Instability in 65 nm CMOSFET Devices,” 2009 International Electron Devices and Materials Symposium (IEDMS), Taoyuan, Taiwan, R.O.C.
  7. J. S. Chiu, Chyuan-Haur Kao, Hsian Chen, P. Y. Tsung, Y. C. Liao, W. S. Liao, Y. T. Chung, H. C. Fan, P. L. Lai, C. Y. Huang, C. S. Lin, J. M. Dai, Electrical and Physical Characteristics of the High-K Gd2O3 (Gadolinium) Dielectric Deposited on the Polycrystalline Silicon,” 2009 SSDM (Solid State Device Meeting), Sendai, Japan.
  8. J. S. Chiu, Chyuan. Haur. Kao, C. S. Chen, T. C. Chan, K. S. Chen,W. S. Luo, Y. T. Chung, C. C. Ou,” High-K Ta2O5 Polyoxide Deposited on Polycrystalline with NH3 Plasma Treatment,” 2009 215th ECS (Electrochemical Society) Meeting (2009), San Fancisco, USA.
  9. T. C. Chan, Chyuan. Haur. Kao, C. H. Lee, J. S. Chiu, S. K. Chen, Y. T. Chung, W. S. Luo,” Oxide Grown on Metal Induced Crystallization Polysilicon Combined with CF4 plasma Treatment,” 2008 International Electron Devices and Materials Symposium (IEDMS), Taichung, Taiwan, R.O.C.
  10. C. S. Chuang, Chyuan. Haur. Kao, C. S. Lai, M. C. Tsai, K. S. Chen, S. K. Chen, H. C. Fan, S. P. Lin, C. R. Chen, ” Fabrication of Germanium Nanocrystals by Rapid Thermal Annealing,” 2008 International Electron Devices and Materials Symposium (IEDMS), Taichung, Taiwan, R.O.C.
  11. K. S. Chen, Chyuan. Haur. Kao, Hsin-Ming Hou, C. S. Chuang, S. K. Chen, H. C. Fan, S. P. Lin, T. J. Li,” Hot Carrier Induced Degradation for Nanometer MOSFET Device”, 2008 International Electron Devices and Materials Symposium (IEDMS), Taichung, Taiwan, R.O.C.
  12. J. S. Chiu, Chyuan. Haur. Kao, C. S. Chen, T. C. Chan, W. S. Luo, Y. T. Chung,” High-K Ta2O5 Polyoxide Deposited on Polycrystalline with NH3 Plasma Treatment,” 2008 International Electron Devices and Materials Symposium (IEDMS), Taichung, Taiwan, R.O.C.
  13. Chyuan-Haur Kao, C. H. Lee, T. C. Chan, J. S. Chiu, C. S. Chen, K. S. Chen, C. S. Chuang, S. K. Chen, “Polyoxide Grown on Metal Induced Re-crystallized Polysilicon Combined with CF4 Plasma,” 2008 IEEE ICSICT 9th International Conference on Solid-State and Integrated-Circuit Technology, Beijing, China.
  14. Chyuan. Haur. Kao, C. H. Lee, T. C. Chan, S. K. Chen, “Oxide Grown on Polycrystalline Silicon by Metal Induced Crystalization,” 2008 Sixth Asian Conference on Electrochemistry, Taipei, Taiwan, R.O.C.
  15.  J.C. Liao, Y.K. Fang, and Chyuan. Haur. Kao,A Systematic Study of the Static and Dynamic Negative Temperature Instability on Low-Temperature Polycrystalline Silicon (LTPS) Thin Film Transistors,” 2008 Sixth Asian Conference on Electrochemistry, Taipei, Taiwan, R.O.C.
  16. Chyuan. Haur. Kao, C. S. Lai, M. C. Tsai, K. S. Chen, T. C. Chan, C. S. Chuang, S. K. Chen, “Using Rapid Thermal Annealing for Ge Nanocrystals Formation,” 2008 Sixth Asian Conference on Electrochemistry, Taipei, Taiwan, R.O.C.
  17. Chyuan Haur Kao, C. S. Lai, M. C. Tsai, C. H. Lee, H. C. Huang, C. R. Chen, “Ge-Nanocrystal Fabricated by Thermal Oxidation and Rapid Thermal Annealing on Polycrystalline-SiGe,” 2008 Material Research Society (MRS) Spring Meeting, San Fancisco, USA.
  18. Chyuan Haur Kao, C. S. Lai, W. H. Sung, C. S. Chen, “Negative Bias Temperature Instability for p-channel of LTPS Thin Film Transistors with Fluorine Implantation,” 2008 Material Research Society (MRS) Spring Meeting, SanFancisco, USA.
  19. Chyuan Haur Kao, C. S. Lai, M. C. Tsai, C. H. Lee, H. C. Huang, C. R. Chen, Y. W. Liao, C. S. Chuang, “Ge-Nanocrystal Fabricated by Thermal Oxidation and Rapid Thermal Annealing on Polycrystalline-SiGe,” 2007 International Electron Devices and Materials Symposium (IEDMS), Hsinchu, Taiwan, R.O.C.

NSC 96-2221-E-182-053.

  1. Chyuan Haur Kao, C. S. Lai, W. H. Sung, C. S. Chen, H. C. Huang, C. R. Chen, C. H. Chiu, T. C. Chan, “Negative Bias Temperature Instability for p-channel of LTPS Thin Film Transistors with Fluorine Implantation,” 2007 International Electron Devices and Materials Symposium (IEDMS), Hsinchu, Taiwan, R.O.C.

NSC 96-2221-E-182-053.

  1. 21.      Wen-Hsiang Sung, Chyuan Haur Kao, Hsing-Kan Peng, Shang-Feng Huang, Wen-Fa Tsai, Chi-Fong Ai, Chih-Rong Chen and Chao-Sung Lai, “In-Situ Fluorinated Low-Temperature Polycrystalline Silicon (LTPS) Thin-Film Transistors (TFT) with Low Trapping and Off Current by CF4 Plasma,” 2007 SSDM (Solid State Device Meeting), Tokyo, Japan.
  2. 22.      Chyuan Haur Kao, C. S. Lai, W. H. Sung, “Electrical and Reliability Improvements for Thin-Film Transistor using TEOS Gate Dielectrics with RTN2O Annealing,” 2007 211th ECS (Electrochemical Society) Meeting (2007), Chicago, USA.
  3. 23.      Chyuan Haur Kao, C. S. Lai, M. C. Tsai, C. S. Huang, T. M. Fan, “Fabricated Ge Nanocrystals with Rapid Thermal Annealing on Poly-SiGe,” 2007 211th ECS (Electrochemical Society) Meeting (2007), Chicago, USA.
  4. 24.      Chao Sung Lai, Chen Sheng Huang, K. M. Fan, T. M. Pan, Chyuan Haur Kao,  Z. G. Lin, C. S. Chang, and C.-P. Chou, “Nano-Charge-Trapping Devices Fabricated by One-Step Oxidation on Poly-SixGe1-x,“ 2006 IEEE SILICON NANOELECTRONICS WORKSHOP, Honolulu, HI, USA.
  5. Chyuan Haur Kao, C. S. Lai, W. H. Sung and H. K. Peng, ”Etching Enhancement of HfO2 by SF6 with O2 Ion-Bombardment”, 2006 International Electron Devices and Materials Symposium (IEDMS), Tainan, Taiwan, R.O.C.

 

 

 

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