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長庚大學 電子工程學系
勤勞樸實 追求卓越
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周煌程副教授

周煌程

副教授

 

組別

硬體系統晶片

電話

5781

Email

hcchow@mail.cgu.edu.tw

實驗室

產業應用實驗室(工學院9樓)

學歷

  • 台灣大學電機工程博士 ( 1992/12)
  • 台灣大學電機所碩士班 ( 1989/9 )  
  • 台灣大學電機工程學士 ( 1988/6 )  

經歷

  • 長庚大學副教授 ( 1999/8 -  )
  • 電子系副系主任、在職專班主任
  • 工研院電通所子計畫負責人、IC設計工程師、專利審查委員
  • 微控制器技術及專利技術移轉
  • 工研院鼓勵創新應用研究計畫負責人
  • 台大電機所博士後研究

開授課程

98學年度第二學期

專長與研究領域

  • 類比/數位/混合訊號積體電路設計
  • 生醫積體電路設計與應用
  • 半導體元件及電路延遲模型

簡歷

Chow, Hwang-Cherng received his B.S. and Ph.D. degrees in Electrical Engineering from National Taiwan University, Taiwan, Republic of China, in June 1988 and December 1992, respectively.

Dr. Chow was with CCL/ITRI as a sub-project leader and a circuit designer from 1993 to 1999. Since August 1999 he has been at the faculty of Chang Gung University, where he is currently an associate professor in the department of Electronics Engineering.  Dr. Chow’s research interests include analog/digital/mixed-signal IC design, biomedical circuits and applications, and semiconductor device and circuit delay models.

著作列表

研究獎勵及榮譽

1. 工研院電通所 專利應用獎3次

2. 兩項專利列入``電通所十大應用專利”,應用在微控制器系列產品

3. 工研院優良創新應用研究獎

4. 工研院電通所 第四屆創新獎

5. Who’sWho in Science and Engineering (Marquis), 2001

6. Who’sWho in the World (Marquis), 2001

7. 教育部92學年度IC設計競賽 研究所全客戶組 優等(全國第二名),2004

8. Who’sWho in Asia (Marquis), 2006

9. 2006工研院優質專利獎

10. 2007工研院優質專利獎

 

Journal articles & book chapters:

1. H.-C. Chow, “A simple I/O buffer for mixed voltage applications”, WSEAS Transactions on Electronics, no.2, vol. 2, pp. 62-65, April 2005

2. H.-C. Chow, “Duty cycle adjusting circuit for clock signals”, WSEAS Transactions on Electronics, no.2, vol. 2, pp. 66-71, April 2005

3. H.-C. Chow, “Speed-enhanced CMOS level shifting circuits for VLSI applications”, WSEAS Transactions on Electronics, no.2, vol. 2, pp. 72-76, April 2005

4. H.-C. Chow, I.-C. Wey and H.-C. Liang, “High speed pipelined Booth multiplier”, WSEAS Transactions on Circuits and Systems, no.5, vol. 4, pp. 495-506, May 2005

5. H.-C. Chow, “Low cost frequency doubler circuits and dividers using duty cycle control buffers”, WSEAS Transactions on Circuits and Systems, no.6, vol. 4, pp. 618-625, June 2005

6. H.-C. Chow, C. Huang and H.-C. Liang, “Low noise high and low speed output buffer design for USB applications”, WSEAS Transactions on Circuits and Systems, no.6, vol. 4, pp. 626-633, June 2005

7. H.-C. Liang, J.-M. Jang and H.-C. Chow, “Speeding up failure shape analysis for memory diagnosis”, WSEAS Transactions on Circuits and Systems, no.6, vol. 4, pp. 634-641, June 2005

8. H.-C. Chow and J.-B. Hsiao, “A new CMOS image sensor for low voltage and low power applications”, WSEAS Transactions on Circuits and Systems, no.8, vol. 5, pp. 1335-1341, Aug. 2006

9. H.-C. Chow and N.-L. Yeh, “A new phase-locked loop with enhanced lock-in design”, WSEAS Transactions on Circuits and Systems, no.8, vol. 5, pp. 1323-1328, Aug. 2006

10. H.-C. Chow and C.-H. Su, “A new all-digital phase-locked loop with high precision and low jitter”, Vol. 95, No. 12, pp. 1241-1249, International Journal of Electronics, Dec. 2008

11.  H.-C. Chow and C.-L. Hsieh, “High speed charge transfer sense amplifier for 0.5V DRAM array applications”, International Journal of Electronics, pp. 165-171, No. 2, Vol. 96, Feb. 2009

 

12.  H.-C. Chow and W.-S. Feng, “Analytical delay model of CMOS inverter including channel length modulations”, IEE Electron. Lett, vol. 28, pp. 408-410, Feb. 13, 1992

13.  H.-C. Chow, W.-S. Feng and J. B. Kuo, “Simple analytical model for short-Channel MOS devices”, IEE Proc., Part G, vol. 139, pp. 405-409, June 1992

14.  H.-C. Chow and W.-S. Feng, “Model for propogation delay evaluation of CMOS Inverter including input slope effects”,IEE Electron. Lett, vol. 28, pp. 1159-1160, June 1992

15.  H.-C. Chow and W.-S. Feng, “An analytical CMOS inverter delay model Including channel length modulations”, IEEE J. Solid-State Circuits, vol. 27, No. 9, pp.1303-1306, Sept. 1992

16.  H.-C. Chow, W.-S. Feng and J. B. Kuo, “An improved analytical short-channel MOSFET model valid in all regions of operation for analog/digital circuit Simulation”, IEEE Trans. CAD, vol. 11, no. 12, pp. 1522-1528, Dec. 1992

17.  H.-C. Chow and W.-S. Feng, “An improved analytical model for short-channel MOSFET’s”, IEEE Trans. Electron. Devices, vol. 39, no. 11 , pp. 2626-2629, Nov. 1992

18.  H.-C. Chow, “Delay analysis of a short-channel CMOS inverter”, CCL Technical Journal, vol. 26, pp. 58-63, ITRI, Feb. 1994.

19. H.-C. Chow, “CMOS output buffer design”, CCL Technical Journal, vol.52, pp. 72-77, ITRI, Sept. 1996.

20.   H.-C. Chow, “CMOS level shifting circuit design”, CCL Technical Journal, vol. 62, pp. 3-9, ITRI, Sept. 1997.

21. H.-C. Chow, “Bidirectional buffer design for mixed voltage applications”, CCL Technical Journal, vol. 72, pp.  10-14, ITRI, Sept. 1998.

22. H.-C. Chow and W.-S. Feng, “New symmetrical buffer design for VLSI applications”, International Journal of Electronics, vol. 88, pp. 779-787, July 2001

23. H.-C. Chow and I-H. Wang, “High performance automatic gain control circuit for communication applications”, WSEAS Transactions on Systems, no. 4, vol. 3, pp. 1820-1824, June 2004

24. H.-C. Chow and C.-S. Hsu, “New voltage level shifting circuits for high performance CMOS interface applications”, WSEAS Transactions on Circuits and Systems, no. 4, vol. 3, pp. 975-979, June 2004

25. H.-C. Chow and Y.-K. Ho, “A new CMOS image sensor with pixel-shared design and split-path readout circuit”, WSEAS Transactions on Circuits and Systems, no. 5, vol. 3, pp. 1252-1256, July 2004

26. H.-C. Chow, I.-C. Wey and C.-H. Huang, “A new low voltage CMOS 1-bit full adder for low power applications”, WSEAS Transactions on Circuits and Systems, no. 5, vol. 3, pp. 1246-1251, July 2004

International Conference & proceeding papers:

1. H.-C. Chow et al., “A 1.8V 0.3mW 10-bit SA-ADC with new self-timed timing control for biomedical applications”, ISCAS, 2005.

2. H.-C. Chow and N.-L. Yeh, “A new phase-locked loop with high speed phase frequency detector”, International Midwest symposium on circuits and systems, 2005/8.

3.  H.-C. Chow and J.-B. Hsiao, “A new rail-to-rail readout circuit for CMOS image sensor for low power applications”, International Midwest symposium on circuits and systems, 2005/8.

4. H.-C. Chow and W.-W. Sheen, “Low power LVDS circuit for serial data communications”, ISPACS 2005, pp. 293-296, Dec. 2005.

5. H.-C. Chow and J.-H. Huang, “A faster-locking pulse width control loop with voltage limited charge pump”, 2006 RISP International workshop on nonlinear circuits and signal processing, pp. 275-278, March 2006.

6. H.-C. Chow and C.-H. Su, “A high precision all-digital phase-locked loop with low power and low jitter”, The 4th IASTED International conference on circuits, signals and systems, pp. 47-51, Nov. 2006.

7. H.-C. Chow and J.-Y. Wang, “High CMRR instrumentation amplifier for biomedical applications”, IEEE International symposium on signal processing and its applications, 2007/2.

8. H.-C. Chow and Y.-G. Chen, “A low noise and reliable CMOS I/O buffer fir mixed low voltage applications”, WSEAS international conference on microelectronics, nanoelectronics and optoelectronics, pp. 32-36, 2007/5.

9. H.-C. Chow and C.-L. Hsieh, “A 0.5V high speed DRAM Charge Transfer Sense Amplifier”, IEEE International Midwest symposium on circuits and systems, pp. 1293-1296, 2007/8.

10. H.-C. Chow and Y.-H. Chen, “ 1V 10-bit successive approximation ADC for low power biomedical applications”, IEEE European conference on circuit theory and design, pp. 196-199, 2007/8.

11. H.-C. Chow and P.-N. Weng, “A low voltage rail-to-rail OPAMP design for biomedical signal filtering applications”, IEEE International symposium on electronic design, test and applications, 2008/1.

12. H.-C. Chow and J.-C. Lin, “0.5-V INSTRUMENTATION AMPLIFIER FOR BIOMEDICAL APPLICATIONS”, IADTED Circuits and Systems 2008, Aug. 2008.

13. H.-C. Chow and Z.-H. Hor, “A High Performance Peak Detector Sample and Hold Circuit for Detecting Power Supply Noise”, IEEE APCCAS 2008, pp. 672-675, Nov. 2008.

14. H.-C. Chow and H. Huang, “12-bit Successive Approximation ADC for Low Power Biomedical Applications”, World Congress on Bioengineering, July 2009.

15. H.-C. Chow and W.-T. Lin, “1V 12-bit Low Power Successive Approximation ADC for Biomedical Applications”, 2010 RISP International workshop on nonlinear circuits, communications and signal processing, Mar. 2010.

 

16. H.-C. Chow and W.-S. Feng, “A short-channel propagation delay model suitable for timing verification”, The 1s IEEE Asia-Pacific Conference on Circuits and Systems, pp. 448-453, Dec. 1992.

17. H.-C. Chow, “Bidirectional buffer for mixed voltage applications”,IEEE International Symposium on Circuits and Systems, pp. 270-273, May 1999.

18. H.-C. Chow, “Duty cycle control circuit and applications to frequency Dividers”, IEEE International Conference on Electronics, Circuits and Systems, pp. 1619-1622, Sept. 1999.

19.  H.-C. Chow and W.-S. Feng, “Novel symmetrical buffer design for VLSI applications”, 43rd IEEE Midwest Symposium on Circuits and Systems, pp. 176-179, Aug. 2000.       

20.  H.-C. Chow, C.-Y. Huang and C.-H. Chang, “Novel output buffer designs for universal serial bus IC applications”, 7th IEEE International Conference on Electronics, Circuits and Systems, pp. 3-6, Dec. 2000.

21.  H.-C. Chow and I.-C. Wey, “A 3.3V 1GHz high speed pipelined Booth multiplier”, ISCAS, vol. 1, pp.457-460, May 2002.

22.  H.-C. Chow and Y.-K. Ho, “New pixel-shared design and split-path readout of CMOS image sensor circuits”, ISCAS, vol. 4, pp. 49-52, May 2002.

23.  H.-C. Chow and I.-H. Wang, “High performance automatic gain control circuit using a S/H peak-detector for ASK receiver”,ICECS, pp.429-432, Sept. 2002.

24.  H.-C. Chow and I.-C. Wey, “A 3.3V 1GHz low-latency pipelined Booth multiplier with new Manchester carry bypass adder”, ISCAS, pp.V-121-V-124, May 2003.

25.  H.-C. Chow and S.-H. Chang, “High performance sense amplifier circuit for low power SRAM application”,  ISCAS,  pp. 741-744, May 2004.

26.  H.-C. Chow and C.-S. Hsu, “New voltage level shifting circuits for low power CMOS interface applications”, International Midwest Symposium on Circuits and Systems, pp. I-533-I-536, July 2004

27.  H.-C. Chow and Y.-G. Chen, “A reliable and high voltage compatible CMOS I/O buffer”, International Midwest Symposium on Circuits and Systems, pp. III-451-III-454, July 2004

28. H.-C. Chow, “Low cost frequency doubler circuit using duty cycle Control buffer”,IEEE International Analog VLSI Workshop, pp. 185-189, May 1999.

29. H.-C. Chow and C.-Y. Huang, “Novel output buffer design for universal serial bus applications”, 2nd IEEE Asia-Pacific Conference on ASICs, pp. 69-72, Aug. 2000.

30. I.-C. Wey, C.-H. Huang and H.-C. Chow, “A new low voltage CMOS 1-bit full adder for high performance applications”,AP-ASIC, pp. 21-24, Aug. 2002.

31. I.-C. Wey, H.-C. Chow, Y.-G. Chen and A.-Y. Wu, “A fast and power-saving self-timed Manchester carry-bypass adder for Booth multiplier-accumulator design”, AP-ASIC, pp. 50-53, Aug. 2004

 

Patents:

1.周煌程、謝長霖,電荷轉移式感測放大器,中華民國專利I306261, 2009/2

2. 周煌程、何志浩,積體電路電壓源雜訊偵測器,中華民國專利I308960, 2009/4

3. 周煌程, 王佳煜, 馮武雄, High CMRR biomedical instrumentation amplifier,

美國核准專利, 2010/4/9

4. 周煌程, 王佳煜, 馮武雄,200625795 生醫訊號儀表放大器 2006/03/31, (中華民國專利申請中)

5. 周煌程, 陳奕宏, 馮武雄,200726094 類比數位轉換器 2007/02/15, (中華民國專利申請中)

 

1. H.-C. Chow, “CMOS level shifter with steady-state and transient drivers”,US   

patent#5,781,026, July 1998.

2.    H.-C. Chow, ”CMOS level shifting circuit”, US patent #5,698,993, Dec. 1997.

3.    H.-C. Chow, ”CMOS bidirectional buffer without enable control Signal”,US patent #5,808,492, Sept. 1998.

4. H.-C. Chow, “CMOS output buffer with reduced Ldi/dt noise”, US patent #  5,708,386, Jan. 1998.

5. H.-C. Chow, “CMOS output buffer having a high current driving capability With  low noise”,US patent #5,854,560, Dec. 1998.

6.    H.-C. Chow and T.-S. Wu, “Low power consumption oscillators with output Level shifters”, US patent #5,757,242, May 1998.

7.      H.-C. Chow, “具有穩態及暫態推動電路的CMOS電位位準轉換器”, ROC Patent #085218, Aug. 1997.

8.  H.-C. Chow, “CMOS電位位準轉換電路”, ROC patent #082568, Apr. 1997.

9.     H.-C. Chow, “一個不需要輸出置能控制信號的CMOS雙向緩衝器”, ROC Patent #082932, May 1997.

10. H.-C. Chow, “一個具有降低Ldi/dt雜訊電壓的輸出緩衝器”, ROC patent #084660, July 1997.

11. H.-C. Chow, C.-Y. Huang and T.-S. Wu, “High and low speed output buffer    With controlled slew rate”, US patent #5,850,159, Dec. 1998.

12. H.-C. Chow, “CMOS bidirectional buffer for mixed voltage applications”, US patent #5,917,348, June 1999.

13. H.-C. Chow, “一個具有延長信號長度及降低穩態功率消耗的電壓起始重置 電路”,

ROC patent #100,942, Jan. 1999.

14.  H.-C. Chow and T.-S. Wu, “低功率消耗的振盪器電路”, ROC patent #102,655, Aug. 1999.

15. H.-C. Chow, C.-C. Shuai and Y.-H. Chu, “兼具除頻功能的duty cycle控制電路”, ROC patent #104,419,

Nov. 1999.

16. H.-C. Chow, “Voltage regulation circuit with adaptive swing clock scheme”, US patent #6,002,599, Dec. 1999.

17. H.-C. Chow, “適合作不同電壓介面應用的CMOS雙向緩衝器”, ROC patent #110,212,  Apr. 2000.

18. H.-C. Chow and C.-H. Chien, “Bidirectional buffer with active pull up/latch circuit for mixed voltage applications”, US patent #6,060,906, May 2000.

19. H.-C. Chow, C.-C. Shuai and Y.-H. Chu, “Duty cycle control buffer circuit with selective frequency dividing function”, US patent #6,060,922, May 2000.

20. H.-C. Chow, Y.-H. Chu and C.-C. Shuai, “倍頻電路及方法”, ROC patent #108,954,  Mar. 2000.

21. H.-C. Chow, “具有快速及慢速操作控制的大推力CMOS輸出緩衝器”, ROC patent #107,967,  Feb. 2000.

22. C.-Y. Huang, H.-C. Chow and T.-S. Wu, “具輸入訊號變化速率控制的高速及慢速之輸出緩衝器”, ROC patent #111,840,  June 2000.

23. H.-C. Chow, “High drive CMOS output buffer with fast and slow speed controls”,

US patent #06,094,086, July 2000.

24.  H.-C. Chow, “使用可適性時脈信號振幅調整的穩壓電路”, ROC  patent#115,829, Oct. 2000.

25.  H.-C. Chow and C.-H. Chien, “使用主動式推動或栓鎖電路作為不同電壓介面應用的雙向緩衝器”, ROC patent #115,962, Oct. 2000.

26.  H.-C. Chow, Y.-H. Chu and C.-C. Shuai, “Frequency multiplication circuit”, US patent #6,198,317,  Mar.  2001.

27.  H.-C. Chow, “一個具有大電流推動能力及低雜訊的CMOS輸出緩衝器”, ROC Patent #121,040,  Feb.  2001.

28.  H.-C. Chow, Y.-H. Chu and C.-C. Shuai, “Frequency multiplication circuit and Method”, Germany patent #DE 198 22 373 C2, May 2001.

29.  H.-C. Chow, “一個使用本質導電型的拉高電位元件之位準轉換介面電路”, ROC Patent #143,110,  Feb.  2002.

30.  H.-C. Chow, C.-C. Shuai and Y.-H. Chu, “Duty cycle control buffer circuit with selective frequency dividing function”, Germany patent #198 22 374, March 2002.

31. H.-C. Chow, “一個對雜訊具有提高免疫力的電壓起始重置電路”, ROC Patent #155,095, Aug. 2002.

other:

1. 生醫訊號轉換應用的全差動連續近似ADC電路, e科技雜誌, 2005/2

2. 低電壓應用CMOS主動影像感測器電路設計, e科技雜誌, 2006/3

3. 運用新微調單元的全數位鎖相迴路之設計, e科技雜誌, 2006/4

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