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長庚大學 電子工程學系
勤勞樸實 追求卓越
分類清單
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著作列表_陳元賀老師

Publications of Yuan-Ho Chen

 

Journal Papers:

 

J1.        Yuan-Ho Chen* and Yun-Hua Tseng, “Low-cost Multi-standard Video Transform Core Using Time-distribution Scheme,” Electron. Lett., vol. 52, issue 24, pp. 1980-1982, Nov. 2016.  (SCI)

J2.        Yun-Hua Tseng, Yuan-Ho Chen*, Tze-Yang Kao, and Chih-Wen Lu,Low-cost Multi-Standard Simultaneous Forward and Inverse Video Transform Core,” International Journal of Circuit Theory and Applications, vol. 44, issue 8, pp. 1572-1588, Aug. 2016. (SCI)

J3.        Wen-Quan He, Yuan-Ho Chen*, and Shyh-Jye Jou, “Dynamic Error-compensated Fixed-Width Booth Multiplier Based on Conditional-Probability of Input Series,” Circuits Syst. Signal Process., vol. 35, no. 8, pp. 2972-2991, Aug. 2016. (SCI)

J4.        Ping-Yeh Yin, Chih-Wen Lu*, Yuan-Ho Chen, Hsin-Chin Liang, and Sheng-Pin Tseng “A 10-Bit Low-Power High-Color-Depth Column Driver with Two-Stage Multi-Channel RDACs for Small-Format TFT-LCD Driver ICs,” IEEE Journal of Display Technology, vol. 11, no. 12, pp. 1061-1068, Dec. 2015. (SCI)

J5.        Szi-Wen Chen* and Yuan-Ho Chen, “Hardware Design and Implementation of a Wavelet De-noising Procedure for Medical Signal Preprocessing,” Sensors, vol 15, pp. 26396-26414, Oct. 2015. (SCI)

J6.        Yuan-Ho Chen*, “Area-Efficient Fixed-Width Squarer with Dynamic Error-Compensation Circuit,” IEEE Trans. Circuits Syst. II., vol. 62, no. 9, pp. 851-855, Sep. 2015. (SCI)

J7.        Wen-Quan He, Yuan-Ho Chen*, and Shyh-Jye Jou, “High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation,” IEEE Trans. Circuits Syst. I. , vol. 62, no. 8, pp. 2052-2061, Aug. 2015. (SCI)

J8.        Yuan-Ho Chen* and Chieh-Yang Liu, “Area-efficient Video Transform for HEVC Applications,” Electron. Lett., vol. 51, no. 14, pp. 1065-1067, Jul, 2015. (SCI)

J9.        Yuan-Ho Chen*, “An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 1, pp. 203-207, Jan. 2015. (SCI)

J10.   Yuan-Ho Chen*, Ruei-Yuan Jou, Tsin-Yuan Chang, and Chih-Wen Lu, “A High-Throughput and Area-Efficient Video Transform Core with a Time Division Strategy,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 11, pp. 2268-2277, Nov. 2014. (SCI)

J11.   Yuan-Ho Chen* and Hsiao-Tzu Liu, “Hardware-Efficient Multi-Standard Video Transform Core,” J. Circuits Syst. Comput., vol. 23, no 8, 1450119, 2014. (SCI)

J12.   Yuan-Ho Chen*, “Low-cost fixed-width squarer by using a probability-compensated circuit,” Electron. Lett., vol. 50, no. 11, pp. 795-797, May 2014. (SCI)

J13.   Yuan-Ho Chen*, Chih-Wen Lu, Shian-Shing Shyu, Chung-Lin Lee, and Ting-Chia Ou, “A Multi-stage Fault-tolerant Multiplier with Triple Module Redundancy (TMR) Technique,” J. Circuits Syst. Comput., vol. 23, no 5, 1450074, 2014. (SCI)

J14.   Wen-Quan He, Yong-Ming Chang, and Yuan-Ho Chen*, “High-Throughput Rate FFT VLSI Implementation on Linear Array Based Design,” Journal of Advanced Engineering, vol. 9, no 2, pp. 87-92, Apr. 2014.

J15.   Yuan-Ho Chen*, Jyun-Neng Chen, Tsin-Yuan Chang, and Chih-Wen Lu, “High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 3, pp. 463-474, Mar. 2014. (SCI)

J16.   Yuan-Ho Chen* and Tsin-Yuan Chang, “A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 4, pp. 655-664, Apr. 2012. (SCI)

J17.   Yuan-Ho Chen* and Tsin-Yuan Chang, “A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers,” IEEE Trans. Circuits Syst. I, vol. 59, no. 3, pp. 594-603, Mar. 2012. (SCI)

J18.   Chung-Yi Li*, Yuan-Ho Chen, Tsin-Yuan Chang, Lih-Yuan Deng, and Kiwing To, “Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 2, pp. 385-389, Feb. 2012. (SCI)

J19.   Yuan-Ho Chen*, Tsin-Yuan Chang, and Chung-Yi Li, “Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias,” IEEE J. Emerging Sel. Topics Circuits Syst., vol. 1, no. 3, pp. 277-288, Sep. 2011. (SCI)

J20.   Chung-Yi Li*, Yuan-Ho Chen, Tsin-Yuan Chang, and Jyun-Neng Chen, “A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications,” IEEE Trans. Circuits Syst. II, vol. 58, no. 4, pp. 215-219, Apr. 2011. (SCI)

J21.   Yuan-Ho Chen*, Tsin-Yuan Chang, and Chung-Yi Li, “High Throughput DA-based DCT with High Accuracy Error-Compensated Adder Tree,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 4, pp. 709-714, Apr. 2011. (SCI)

J22.   Bor-Sen Chen*, Bore-Kuen Lee, and Yuan-Ho Chen, “Power Control for CDMA Cellular Radio Systems via  Optimal Predictor,” IEEE Trans. Wireless Commun., vol. 5, no. 11, pp. 2914-2922, Oct. 2006. (SCI)

J23.   Bore-Kuen Lee, Yuan-Ho Chen, and Bor-Sen Chen*, “Robust  Power Control for CDMA Cellular Communication Systems,” IEEE Trans. Signal Processing, vol. 54, no. 10, pp. 3947-3956, Oct. 2006. (SCI)

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